Semiconductor memory devices, in general, may be classified as either volatile or non-volatile semiconductor memory devices. Volatile semiconductor memory devices, such as dynamic random access memory (DRAM) devices and/or static random access memory (SRAM) devices, may have a relatively high response speed. However, volatile semiconductor memory devices may lose stored data when power is shut off. Although non-volatile semiconductor memory devices, such as electrically erasable programmable read only memory (EEPROM) devices and/or flash memory devices, may have a relatively slow response speed, non-volatile semiconductor memory devices may enable data to not be lost when power is shut off.
In EEPROM devices, data may be electrically stored, e.g., programmed and/or erased through a Fowler-Nordheim (F-N) tunneling mechanism and/or a channel hot electron injection mechanism, for example. A flash memory device may be classified as either a floating gate type or a charge trip type, such as silicon-oxide-nitride-oxide-semiconductor (SONOS) type devices and/or metal-oxide-nitride-oxide-semiconductor (MONOS) type devices.
SONOS and MONOS type non-volatile memory devices may include a tunnel insulating layer formed on a channel region of a semiconductor substrate, a charge trapping layer for trapping electrons from the channel region, a blocking layer formed on the charge trapping layer, a gate electrode formed on the blocking layer, spacers formed on side surfaces of the gate electrode and source/drain regions formed at surface portions of the semiconductor substrate adjacent to the channel region, for example.
A silicon nitride layer may be used as the charge trapping layer. However, defect sites, such as silicon dangling bonds, silicon hydrogen (Si—H) bonds, etc, may be present in the silicon nitride layer and may cause lateral charge diffusion. As a result, data retention performance and/or reliability of the non-volatile memory device may be deteriorated.
A conventional non-volatile memory device may serve a single level cell (SLC) or a multi-level cell (MLC), and electrically perform programming and/or erasing operations using the F-N tunneling mechanism and/or the channel hot electron injection mechanism, for example.
When a conventional non-volatile memory device is used as the SLC, a logic stage of “0” or “1” may be stored in the charge trapping layer.
When a conventional non-volatile memory device is used as the MLC, a logic stage of “00,” “01,” “10” or “11” may be stored in the charge trapping layer.
When a conventional non-volatile memory device is used as the MLC, a relatively high thermal and/or electrical stress may be applied to a conventional non-volatile memory device compared to when a conventional non-volatile memory device is used as the SLC. Thus, when a conventional non-volatile memory device is used as the MLC, a threshold voltage window of about 6.0V may need to be applied.
To increase a threshold voltage window of a conventional non-volatile memory device, a metal oxide layer having a dielectric constant higher than that of silicon nitride may be used as the blocking layer. For example, an aluminum oxide layer may be used as the blocking layer.
However, an unwanted material layer may be formed between a silicon nitride layer used as the charge trapping layer and the aluminum oxide layer while forming the aluminum oxide layer. For example, an aluminum silicon oxynitride layer may be formed between the silicon nitride layer and the aluminum oxide layer. Thus, the threshold voltage window of the non-volatile memory device may be decreased by the aluminum silicon oxynitride layer. For example, while performing a programming and/or erasing operation of the non-volatile memory device, an electric field applied to the tunnel insulating layer may be decreased by the aluminum silicon oxynitride layer. Thus, the threshold voltage window may be decreased. As a result, the reliability of a non-volatile memory device may be deteriorated.